Field programmable gate arrays (FPGAs) are integrated circuits that can achieve an arbitrary logical function. An FPGA includes logic blocks (LBs) that perform arbitrary logical operations, and switch blocks (SBs) that switch connections among the logic blocks. The logic block includes at least one look-up table (LUT) circuit, which outputs a value stored in a memory in response to an input. The look-up table circuit may have a function to switch wiring lines by rewriting the memory. The logic block may also include a flip-flop (FF) circuit and/or a hard macro. The flip-flop circuit may be connected to an output of the look-up table circuit, or directly connected to an input terminal of the logic block. The hard macro herein means a pre-designed circuit group. Examples of the hard macro include a half adder including an AND gate and an XOR gate, and a full adder additionally including an OR gate.
An arbitrary operation circuit and/or a wiring line connection of the FPGA may be achieved by means of a memory value written to a cell of a configuration memory. If a memory value of the LUT circuit is changed, a memory value selected in response to an arbitrary input may be outputted. The configuration memory or the switch block includes a transistor switch, which may be turned on or off by changing the value of the memory connected to its gate. A MUX circuit including a plurality of transistor switches controls a connection between arbitrarily selected input and output by changing the memory value.
Conventional configuration memories include a volatile memory with SRAM cells. The SRAM cell includes two inverter circuits that are cross-coupled. An output of one of the inverter circuits is connected to an input of the other. The memory value may be fixed by providing a value to be written and its inverted bit to access transistor circuits connected to the inputs of the two inverter circuits. The SRAM cells are widely used in configuration memories of FPGAs since they may be formed by a standard CMOS process, and the memory values of the SRAM cells may be easily rewritten.
However, the SRAM cells are volatile cells, and the memory values stored in them are erased when the power is turned off. Furthermore, there is a possibility that a soft error may be caused in the SRAM cells, in which the memory values are changed due to noise. If a soft error is caused in a file memory, the soft error may be solved by using an error check and correct (ECC) memory. However, in an FPGA, the memory value is directly reflected in the operation of the logic circuit, and therefore it is difficult to provide an ECC to the FPGA. Furthermore, if a soft error occurs in an FPGA, the content of an operation changes, which greatly affects the operation.
A nonvolatile configuration memory may solve the problem of soft error. There are a large number of examples in which a nonvolatile memory is directly used as a configuration memory. However, a nonvolatile memory generally operates slower than an SRAM memory. Therefore, time and costs incurred in developing a nonvolatile memory may be increased.
There is an example in which an SRAM cell includes a nonvolatile memory to enable the use of both the SRAM cell and the nonvolatile memory. This example has a configuration where floating gate type memory transistors are disposed between access transistors and a memory portion of the SRAM cell. Data is written to one of the floating gate type memory transistors so that it is in a low-resistance state when a read operation is performed. When a High level potential and a Low level potential is given to respective bit lines, a current flows on the side where the memory transistor to which the data is written is present. The value of the SRAM cell is fixed by the value of the memory transistor. In this case, three power supplies for writing data to, erasing data from, and reading data from the memory transistor are needed. In order to control the three power supplies, at least three power supply control systems are needed. Since the memory in this example needs to rewrite the nonvolatile memory, the three power supplies should be provided. Furthermore, since the memory transistor needs to be formed by a process that is different from a standard manufacturing process, additional costs are incurred to form the memory transistors. In addition, the charge retaining nonvolatile memory as described above may lose the memory value if being subjected to noise or a high temperature for a long time.